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| PMC-Sierra,Inc. PM5347 S/UNI-155-PLUS 155 Mb/s SATURN User Network Interface for WANs FEATURES * Monolithic SATURNTM-compatible Asynchronous Transfer Mode (ATM) network interface. * Implements the ATM transmission convergence (TC) sublayer for ATM according to ATM Forum specifications and ITU-T recommendations using the SONET/SDH 155.52 Mb/s format. Also implements ATM Forum specified "Mid-range PHY" rates of 51.52, 25.92 and 12.96 Mb/s. * Includes on-chip clock recovery and clock synthesis at all rates. Clocking can be bypassed for use with external clock sources. Operates in master or slave (loop timed) timing modes. * Provides TTL-compatible inputs and outputs. Provides differential pseudoECL-compatible serial line side inputs. * Supports Fiber Optic, Unshielded Twisted Pair and Shielded interfaces. * Processes all SONET/SDH UNI overhead. * Provides access to section and line datalinks and all additional transport and path overhead to allow additional external processing for full SONET/ SDH Network-Node Interface (NNI) compliance. * Provides synchronous 8-bit or 16-bit SCI-PHYTM system side interface with 4-cell deep FIFO buffers in transmit and receive paths with parity support. * Inserts and extracts ATM payloads using cell delineation. * Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. * Software-compatible with the PM5345 S/UNI-155TM, PM5346 S/UNI-155LITETM and the PM5355 S/UNI-622TM. * Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes. * Low power, +5 V CMOS technology. * Packaged in a 208 pin (28mm x 28mm) PQFP with 0.5mm pin pitch. * Industrial temperature range operation (-40C to +85C). * Counts received cells written into the receive FIFO, received HCS errored cells that are discarded, and received HCS errored cells that are corrected and passed through the receive FIFO. PMC-930909 (R7) TRANSMIT SECTION * Counts transmit cells read from the transmit FIFO. * Inserts a register programmable path signal label (C2). * Inserts path B3, path FEBE indications, line B2, line FEBE indications, and section B1 to allow performance monitoring at the far end. * Optionally inserts the 16- or 64-byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence from internal register banks. * Optionally inserts an externally generated section user channel (F1), order wire channels (E1, E2) and the DCC channels (D1-D3 and D4-D12) via serial interfaces. * Optionally inserts path AIS, path RDI, line AIS, and line RDI. * Optionally inserts register programmable APS (K1, K2) and synchronization status (Z1) bytes. * Extracts the 16- or 64-byte section trace (J0) sequence and the 16- or 64byte path trace (J1) sequence into internal register banks. * Extracts the DCC channels (D1-D3 and D4-D12) for optional external processing. * Detects Loss Of Signal (LOS), Out Of Frame (OOF), Loss Of Frame (LOF), line Alarm Indication Signal (AIS), line Remote Defect Indication (RDI-L), Loss Of Pointer (LOP), path AIS, path RDI (RDI-P) and Loss Of Cell Delineation (LCD). * Counts received section B1 errors, line B2 errors, line FEBEs, path B3 errors and path FEBEs for performance monitoring purposes. APPLICATIONS * * * * * ATM Switching Systems ATM Access Systems LAN Switches, Hubs and Routers ATM Test Equipment SONET or SDH ATM Interfaces RECEIVE SECTION * Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure. BLOCK DIAGRAM TSDCLK,TOWCLK TSD,TSOW,TSUC Line Side System Side TLRDI TLDCLK TLD,TLOW TTOH TPOH TPOHFP TPOHCLK TPOHEN TTOHCLK TTOHEN TOHFP POP[3:0] GTOCLK GTOCLK TTOHFP PIP[3:0] TDO TDI TCK TMS TRSTB JTAG Test Access Port TSOC TDAT[15:0] TXPRTY[1:0] TPRDI TPAIS TGFC XOFF TLAIS TBYP TATP Transport O/H Extract Path O/H Extract Parallel Input/Output Port TCP TRCLK+/TXD+/TXC+/RXDO+/RXD+/ALOS+/RRCLK+/- Clock Recovery SIPO Transmit Section O/H Processor Transmit Line O/H Processor Section Trace Buffer Transmit Path Overhead Processor Path Trace Buffer Receive Path Overhead Processor Transmit ATM Cell Processor Transmit ATM 4-Cell FIFO Drop Side I/F TCA TWRENB TFCLK RSOC RDAT[15:0] RXPRTY[1:0] RCA RRDENB Clock Recovery SIPO Receive Section O/H Processor Receive Line O/H Processor Receive ATM Cell Processor Receive ATM 4-Cell FIFO Transport O/H Extract Path O/H Extract Microprocessor Interface RFCLK RTOH BUS8 LF+/- LCD RTOHCLK GROCLK RTOHFP RLDCLK ROHFP RSDCLK,ROWCLK RLD, RLOW RPOH RPOHFP RPOCLK LOP PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1998 PMC-Sierra, Inc. October, RSD,RSOW,RSUC RGFC RBYP TSEN LRDI D[7:0] A[7:0] WRB LOS LAIS ALE RDB RATP RSTB PRDI PYEL INTB RCP CSB LOF FLO PM5347 S/UNI-155-PLUS 155 Mb/s SATURN User Network Interface for WANs TYPICAL APPLICATION 155 Mb/s ATM SWITCH PORT INTERFACE Transmit Alarm Insert Signals Reference Clock Transmit Overhead Insert TRCLK+/E/O TCA TXPRTY[1:0] TDAT[15:0] TSOC PM5347 681,3/86 TXD+/- Transmit ATM Process TWRENB TM TFCLK Switching Network 155 Mb/s SATURN User Network Interface for WANs TM RCA RXPRTY[1:0] RRCLK+/RXD+/O/E RDAT[15:0] RSOC RRDENB RFCLK Receive ATM Process ALOS+/- Receive Overhead Extract Receive Alarm Detect Signals Microprocessor Bus for Configuration, Status, and Control STS-3C/STM-1 OVERHEAD BYTE USAGE Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-930909 (R7) 1998 PMC-Sierra, Inc. October, 1998 SATURN, SCI-PHY, S/UNI-155, S/UNI-155-LITE, S/UNI-155-PLUS, and S/UNI-622 are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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